Cat Swarm Intelligence-Driven Optimization for High Power Factor Single-Stage AC–DC Converters

These days, the uses of AC/DC switch-mode converters, for example, PC control supplies, battery chargers, and other electronic gear, are quickly developing and result in some power quality issues [1, 2]. This hardware comprises of semiconductor gadgets that indicate nonlinear conduct and work at high frequencies [3]. Consequently, these gadgets infuse numerous consonant unsettling influences into the system and lessen the power factor [4]. Lately, new directions have encouraged enthusiasm for Power Factor Correction (PFC) systems for lessen the unsettling influence in the system [5, 6]. The interest for PFC has been expanding for the present disconnected power supplies and even those at low power levels. The disconnected AC-DC device converters utilized in a large portion of the present electrical gear have been a noteworthy wellspring of consonant bending drawing mutilated flow waveforms, dirtying the mains, and accordingly corrupting force quality [7, 8]. Today, a made converter ought to fulfill satisfactory power quality measurements. Power quality issues have dependably been a critical theme in power designing, be that as it might, as of late, this point has drawn an uncommon consideration because of the expanded utilization of elite electronic gadgets [9, 10].

 

With the rising mandate for high-quality power factor systems, power factor improvement has develop a critical aspect in converter design [11]. To address this, both single-stage and two-stage converter topologies are widely adopted. The two-stage configuration offers high power factor and fast output voltage response by employing independent controllers and separate power stages [12, 13]. Nevertheless, the approach suffers from certain key drawbacks the increased cost and bulkiness arising from the complex circuit structure, making it less suitable for low-power applications [14]. To address these boundaries, single-stage clarification systems have been developed that integrate the PFC phase and the DC/DC converter into a unified structure. Typically, these single-stage PFC converters employ a boost topology operating in Discontinuous Conduction Mode to realize effective power factor correction [15]. DCM operation generally results in lower Total Harmonic Distortion (THD) of the input current compared to Continuous Conduction Mode (CCM), although CCM provides slightly higher efficiency than DCM[15].

 

AC–DC converters performance an energetic part in power electronic systems due to their advantages of low cost and ease of implementation [16]. Simultaneously, they lead to multiple operational challenges that can unfavorably impression the system, such as feeder overloading, harmonic distortion, high investment cost, reduced efficiency, and limited reliability, which hinder their extensive adoption [17, 18]. The overall size and cost of a converter largely depend on its regulator strategy, which should ideally be optimized for the best performance. Operating at higher switching frequencies, however, increases transistor switching losses, thereby limiting efficiency. To enhance control and power factor correction (PFC), Frequent performances have been scrutinized in prior research , including Artificial Neural Networks (ANN), Control Lyapunov functions, discrete energy functions, Fuzzy Logic Controllers (FLC) [19], Adaptive Neuro-Fuzzy Inference Systems (ANFIS), Particle Swarm Optimization (PSO), and Genetic Algorithms (GA) [20]. Nevertheless, these methods often struggle to deliver best presentation under fluctuating load circumstances, which leads to degradation in the overall power superiority of the organization and necessitates more effective solutions. In this work, a Cat Swarm Optimization (CSO) constructed control technique integrated with a Fractional Order PID (FOPID) controller is anticipated for achieving optimal PFC in an AC–DC converter. The method regulates the DC association voltage by comparing the actual load voltage with a reference voltage, where the variation over time is processed through the CSO–FOPID framework. Based on these variations, the appropriate switching mode is determined to maintain efficient operation. The usefulness of the anticipated approach is authenticated by comparing the output voltage presentation of the AC–DC converter against existing FA and CS algorithms. The paper is organized as follows: Section 2 discusses related work; Section 3 outlines the proposed methodology and PFC stage operation; Section 4 reports the implementation and simulation results; and Section 5 summarizes the conclusions.

This subdivision offerings the design and description of the PFC strategy for a line-coupled single-stage AC–DC converter. In this approach, an optimal control mechanism is developed specifically for single-stage operation, where The proposed topology integrates both power factor correction (PFC) and DC–DC voltage regulation functionalities into a single-stage configuration. The primary objective of the proposed control system is twofold: to achieve input power factor correction and to regulate the DC-link voltage at the output. To accomplish this, a line-coupled single-stage AC–DC converter is designed, and a novel control strategy is subsequently developed to enhance system performance. The integration of the designed converter with the proposed control scheme results in the realization of an optimal controller for enhanced performance.

 

Fig.1 Structure of proposed single-stage line-coupled AC to DC converter

 

A single-stage line-coupled AC–DC Converter with enhanced power factor capability and ripple-free input current is proposed, as illustrated in Figure 1. In this configuration, the PFC stage and the DC–DC conversion stage are integrated by sharing two active switches, thereby reducing circuit complexity. The practice of a together inductor enables the planned converter to achieve near-unity power factor while ensuring a smooth, ripple-free input current. The switching devices operate with complementary duty cycles, which are modulated to normalize the output voltage. Under AC input conditions, the main inductor and associated circuit elements maintain continuous current flow during switching transitions. In this work, the converter’s input control is regulated to accurately track a predefined reference profile, ensuring that the input current remains in phase with the input voltage and thereby achieving effective power factor correction. This redresses the power factor of information control supply. Here the count of blunder esteem is given as,

 

                                                   (1)

                                                  (2)

 

Equation (2) defines the actual input power distributed to the converter. The proposed control approach adjusts the input current based on this power value, ensuring that it remains directly proportionate to the input voltage which is considered constant throughout the converter’s operation. Consequently, power factor improvement is achieved by aligning the input current waveform with the input voltage waveform. In simpler terms, the input power is regulated to follow its reference value. The resulting error, calculated from equation (1), is then used to generate the control signal for the PWM modulator, which in turn produces the gating pulses required to drive the power switches.

Operation of PFC stage

The future PFC circuit operating modes are illustrated,  and the flows coursing through the channel capacitors and separately.  is the present finishing the inductor . As can be demonstrates the coupled inductor is displayed as the charging inductance and perfect transformer which has a turn proportion of 1:1 [26]. The is the charging inductance has been sufficiently vast to keep up a steady current  inside a switching period.

 

Fig.2 Operating modes of the PFC stage

 

The consistent state task of the PFC circuit in one swapping period incorporates eight modes, as shows in Figure 2. Switches and are worked lopsidedly and the duty ratio depends on the switch . The activity displays symmetry for the two scopes of the responsibility ratio from 0 to 0.5 and from 0.5 to 1. Without loss of simplification, the converter is measured with the duty ratio from 0 to 0.5. To represent the relentless state task, it is expected that all segments are perfect [27]. The swell part of the dc-link voltage is irrelevant on the grounds that the dc-link capacitor has a vast esteem. It is expected that the supply voltage is viewed as littler than the dc-link voltage and steady for an exchanging period. At that point the capacitor current moves toward becoming,

                                                  (3)

Since , . Along these lines, a similar measure of current courses through every one of the capacitors. At the point when is charging, is discharging. Conversely when is charging, is discharging. In this charge exchange, the swell part of the channel capacitor voltages and is immaterial on the grounds that the channel capacitors and have extensive qualities. Subsequently and are viewed as steady. Before Mode 1, the lift inductor current streams with the peak value through and and .

 

Operation of mode 1:

The upper switch is turned off. Then, the inductor current starts to charge and discharge. The voltage across the upper switch increases and the voltage across the lower switch decreases. Since the switch capacitors and associated in parallel with the switches and have a small value. Therefore, the inductor current has constant value.

 

Operation of mode 2:

The voltage , through the lower switch develops zero. Then, the lower diode and the diode are turned on. Since and , the voltage across the coupled inductor and the voltage across the inductor are given by,

                                                (4)

                                                (5)

 

Operation of mode 3:

The lower switch  is turned on. Zero voltage turn on of is achieved because the current has previously flown through the lower diode before the lower switch is turned on.  has only to be turned on before variations its direction. The inductor current and the current increase linearly like mode 2.  The inductor current and the current approach to at the end of mode 3.

 

When the lower switch is turned ON, zero-voltage switching is achieved since the current is already flowing through the corresponding lower diode prior to the switching action. Thus, only needs to be turned ON before the current variations its direction. During this interval, the inductor current  and the load current  increase linearly, similar to the behavior observed in Mode 2. By the end of Mode 3, both the inductor current and the load current gradually approach the reference value .

 

Operation of mode 4:

The primary current of the ideal transformer arrives at and the diode is turned off. Since the current is clamped at , the current and the current are also clamped at . The voltage is fixed to .

 

Operation of mode 5:

The lower switch is turned off. Then, the inductor current starts to discharge and charge. The upper switch voltage decreases and the lower switch voltage increases.

 

Operation of mode 6:

The voltage across the upper switch becomes zero. Then, the diode and the diode are turned on. Since and , the voltage and the voltage  are given by,

                                                         (6)

                                                   (7)

 

Operation of mode 7:

The upper switch is turned on. Zero voltage turn on of the upper switch is achieved similarly in mode 3. The inductor current and the current decrease linearly like mode 6. The current and the current approach to and zero respectively, at the end of mode 7.

 

Operation of mode 8:

The current arrives at zero and the diode is turned off. Since the inductor current is clamped at , the voltage across the inductor is zero and the voltage is fixed to . Then the error value has been minimization of using FOPID controller, which is tuning the gain parameters. The FOPID supervisor has been achieved the reduced the error value and controlling PWM. The detailed process of FOPID controller has been give below,

 

3.2. Description of FOPID controller

The Fractional Order Proportional-Integral-Derivative controller is an advanced extension of the classical PID controller, achieved by applying fractional-order calculus to the integral and derivative components. This generalization offers several performance benefits, such as the complete elimination of steady-state error, enhanced flexibility in tuning gain and phase crossover frequencies, and improved stability margins. In accumulation, the FOPID supervisor demonstrates strong robustness against variations in system dynamics and ensures better attenuation of high-frequency noise. These attributes make it a controlling mechanism strategy for handling complex, nonlinear, and uncertain systems [28].

 

Numerically the FOPID controller can be defined as equation (8),

                (8)

On performing the Laplace transform of the equation (9),

                                               (9)

Where, signifies the gain of proportionality, signifies the gain of Integral, signifies the gain of Derivative and and are the differential-integral's order for FOPID controller as demonstrated in figure 3 (i) where and can be any real numbers.

 

The traditional PID controller can be considered a specific case of the Fractional Order PID controller, obtained by fixing the fractional integral and derivative orders to unity [29]. This demonstrates that the FOPID controller broadens the capabilities of the classical PID by introducing additional notches of autonomy in tuning. As a result, it provides improved flexibility in adjusting system dynamics, thereby enhancing both the reliability and the overall recital of the control system.In addition, the FOPID controller increases system robustness against sudden disturbances, contributing to improved stability. However, unlike the PID controller which requires tuning of three parameters, the FOPID controller involves five parameters, making the design process more challenging. The primary objective of tuning these parameters is to minimize the performance index, thereby improving the stability margin of the hybrid system.

 

This approach improves the damping characteristics of the organization and minimizes deviations in terminal voltage, thereby reducing the error among input and output power. To evaluate controller performance, standard presentation indices such as the Integral of Absolute Error (IAE), Integral of Squared Error (ISE), and Integral of Squared Time Error (ISTE) are employed. These indices, expressed in equations (10), (11), and (12), serve as key measures for assessing system accuracy and stability.

 

                                                            (10)

                                                             (11)

                                                         (12)

 

It is always required to select a reference model to get the error function . The smaller the error function, the closer the controlled system response is to the reference model. In this context, the performance of the FOPID controller can be evaluated using equations (13) and (14).

                       (13)

                       (14)

 Here, is the reference output voltage,  is the output voltage, is the reference power and is the input power of the system.

 

The regulation of FOPID supervisor parameters is accomplished by minimizing an appropriate objective function, where the assortment of the fitness role plays a critical role in determining the usefulness of the optimization. Performance indices such as the Integral of Absolute Error (IAE) and the Integral of Squared Error (ISE) are commonly used to evaluate the dynamic performance and accuracy of control systems., though they often result in longer settling times despite providing low overshoot. To overcome this limitation, the Integral of Squared Time multiplied by Error criterion is sometimes employed, as it enhances transient response; however, it also increases computational complexity and does not always guarantee desired stability. In this work, the FOPID controller parameters are adjusted online using the Cat Swarm Optimization  algorithm, which directly regulates the DC-link voltage, generates the PWM control signals, and minimizes the error for the AC–DC converter.

 

Process of the CSO algorithm for optimization of dc link voltage

A novel meta-heuristic optimization technique inspired by the color-changing behavior of cats is utilized to achieve optimal power factor correction (PFC) in a line-coupled single-stage AC–DC converter, wherein the Cat Swarm Optimization (CSO) algorithm is specifically employed to optimize the DC-link voltage for enhanced performance and efficiency. The controller gain parameters are initially generated randomly, while system variables such as power and voltage are taken as inputs to the algorithm. The primary objective function is defined to minimize both the error value and the DC-link voltage deviation. Once the optimization process is complete, the corresponding gain parameters are obtained and organized into a dataset for further controller design and performance evaluation.In the CSO algorithm process, the improvement and error values are trained and achieve the best results for the FOPID controllers. 

 

Fig.3 The Flow diagram of (i) FOPID controller and (ii) proposed method

 

Established on the controller’s output, transformation algorithms are applied to generate the optimal switching pulses for the AC–DC converter.

 

This section explains the basic working principle of the Cat Swarm Optimization algorithm. The CSO approach is derived from the behavioral patterns of cats [30], which generally devote much of their time to resting and monitoring their environment, conserving energy by limiting unnecessary movements. This characteristic is mathematically represented in the algorithm through two operating modes: the seeking mode, which corresponds to the cat’s alert and observant resting state used for exploration of possible solutions, and the tracing mode, which mimics the cat’s chasing action used for exploitation of promising solutions.

 

Seeking mode: Resting and Observing:

In the CSO algorithm, the seeking mode simulates the behavior of cats during their sleeping state, where they remain vigilant and observe their environment to decide on the next move [31]. This mode is characterized by four essential parameters: the Seeking Memory Pool , which stores possible candidate solutions; the Seeking Range of the Selected Dimension, which specifies the extent of parameter variation; the Count of Dimensions to Change , which determines the number of variables adjusted during the search; and the Self-Position Consideration , which defines whether the cat’s current position should be retained as a candidate solution. Collectively, these parameters allow effective exploration of the solution space.

 

Tracing Mode – Pursuing a Target:

The tracing mode represents the active hunting behavior of cats. In this phase, a cat updates its position by adjusting its velocity in each dimension, thereby moving towards the target solution. This mode emphasizes exploitation, enabling the algorithm to refine promising areas of the search space for optimal results.

 

CSO movement= Seeking mode + Tracing mode

When relating the CSO algorithm to resolve optimization problems, the preliminary step is to type a resolution on the number of individuals or cats to use. Each cat in the population has the following characteristics [32].

* Each cat’s position is defined in an M-dimensional search space.

* Every dimension of the position is associated with a corresponding velocity.

* The fitness of a cat is evaluated based on a predefined fitness function.

* A mode flag is assigned to indicate whether the cat is operating in seeking mode or tracing mode.

 

Steps of the CSO algorithm:

Step 1: Initially, the FOPID supervisor parameters are initiated randomly such as, and respectively. The primary parameters of CSO algorithm create the number of population  with randomly initialize position, velocity within respective boundaries for each cat.

 

Step 2: Based on the value of the Mixture Ratio (MR), each cat is assigned a specific flag to categorize it into either the seeking mode or the tracing mode process.

 

Step 3: Evaluate the fitness value of each cat and record the one with the highest fitness as the best-performing solution.

 

Step 4:Cats are updated according to their assigned flags—those in seeking mode undergo the seeking process, while the others follow the tracing process. The position of each cat in a given dimension is then updated using equation (15).

        (15)

Where, is the velocity of cat x in dimension d,  is the position of the cat, who has the best fitness value, is the position of , is a constant and is A random value within the range [0, 1] is generated to determine the cat’s velocity, enabling it to move through the M-dimensional decision space and record each new position. If the computed velocity exceeds the maximum allowable limit, it is adjusted to the maximum value, after which the new position of each cat is calculated accordingly.

                                                    (16)

Where,  is the new position of cat in dimension and  is the current position of cat x in dimension d respectively.

 

Step 5: Select a new subset of cats based on the mixture ratio (MR) and assign them to the tracing mode, while the remaining cats are allocated to the seeking mode.

 

Step 6: The algorithm then evaluates the termination condition. If the condition is met, the optimization process concludes; otherwise, the procedure iteratively continues by repeating Steps 3 through 5.

 

The CSO algorithm is optimized automatically by seeking mode and tracing mode operation. Because of its flexibility, the CSO algorithm can be used for a wide range of control applications. The Figure 3 (ii) describes the optimization flow of the CSO algorithm for minimize the error values and PFC in the AC to DC converter. The proposed algorithm is implemented in the subsequent section to design an FOPID controller for optimizing the power factor correction (PFC) in a line-coupled single-stage AC–DC converter system. In this control framework, the FOPID controller is trained using the error signals as inputs, and the corresponding control pulse outputs are applied to the PFC stage to regulate the supply voltage. The CSO-generated output serves as the input to the FOPID controller, facilitating the optimization of its gain parameters. A detailed analysis of the experimental results is presented in Section 4.

In this work, a control topology for the AC–DC converter is developed and implemented using the MATLAB/Simulink platform. The proposed scheme integrates the Cat Swarm Optimization  algorithm with a Fractional Order PID controller to minimize error and enhance the efficiency of power factor correction (PFC) in a line-coupled single-stage AC–DC converter. The effectiveness of the controller is examined in the PFC stage, where it significantly progresses the presentation of the boost converter. By optimizing the switching operations, the system achieves precise control pulses, leading to improved stability and efficiency. The equivalent circuit model is used to analyze the operating modes of the boost converter, while the enhanced controller action reduces voltage leakage and ensures smooth operation. The optimized gain parameters generated by the supervisor are practical to the boost switch, ensuring stable and optimized system behavior. The implementation parameters and simulation setup are presented in this section, with results shown in Figure 4(a) and (b). Finally, the presentation of the anticipated technique is associated with existing optimization techniques, such as the Firefly Algorithm (FA) and Cuckoo Search (CS), and a detailed comparison of parameters is provided in Table 1.

 

Fig.4 Simulink model, (a) AC to DC converter (b) Proposed controller

 

Table 1: Implementation parameters of the proposed and existing method

 

Fig.5 The input voltage and input current waveforms of AC to DC converter

 

Figure 5 illustrates the input voltage waveform and the corresponding current drawn by the proposed AC–DC converter controlled by the developed algorithm. It is evident that the input voltage and current are nearly in phase, indicating that the converter achieves a near-unity power factor. The X-axis represents time in seconds, while the Y-axis denotes the input voltage and current. From the X-axis, it is observed that the simulation is carried out for a duration of 0.5 seconds.

 

Fig.6: Performance comparison of main inductor (a) voltage and (b) current

 

The execution of voltage and current waveforms of principle inductor is delineated. Here, the correlation is performed between proposed CSO algorithm, FA, CS calculation based FOPID controller to the converter. From Figure 6 (a) and (b), it says that, for proposed, FA and CS based FOPID controller, the waveforms are having less swells the Proposed CSO based FOPID controller activity.

 

Fig.7 Performance comparison of main switch (a) voltage and (b) current

 

The voltage and current waveforms of the main switch are illustrated in Figure 7. As shown in Figure 7(i), the voltage waveform obtained using the proposed controller is slightly lower compared to that of the PSO-PID controller and the system without a controller. Meanwhile, Figure 7(ii) depicts the current response of the converter, where the CS-FOPID controller achieves a higher current magnitude compared to both the FA-FOPID and the proposed controller configurations.

 

Fig.8 The performance comparison of (a) output DC voltage (b) converter efficiency vs output power

 

In Figure 8 (a), the execution examination of the novel ideal controller is beautifully shown. It is perfectly clear that, for delicate exchanging without the controller the yield voltage bend has pitiably bombed in landing at the set point and its ascent day and age is high and the settling era likewise far surpasses the replication time frame. Presently, the execution of the effectiveness is surveyed and perfectly imagined in Figure 8 (b). The execution examination of the proposed CSO-FOPID controller with FA-FOPID controller, CS-FOPID controller and hard changing to the AC to DC converter is displayed as far as proficiency versus yield control.

This paper presents a Cat Swarm Optimization (CSO) based governor procedure for power factor correction (PFC) in a line-coupled single-stage AC–DC converter. The proposed mechanism strategy aims to achieve optimal converter performance by reducing switching losses and minimizing voltage deviations. By applying optimized PWM switching functions in both boost and PFC operating stages, the method effectively suppresses fault voltages and enhances overall stability. The efficiency of the mechanism performance is validated through implementation in the MATLAB/Simulink environment, where system performance is evaluated in terms of switch voltage and current, inductor voltage, inductance behavior, and overall efficiency. The analysis of the PFC stage demonstrates that the proposed CSO-based approach consistently outperforms conventional methods. Comparative studies with existing algorithms, such as Firefly Algorithm (FA) and Cuckoo Search (CS), further highlight the dominance of the anticipated technique. Simulation results confirm the effectiveness of the CSO procedure in delivering improved dynamic response, reduced error, and enhanced output performance compared to other methodologies.

 

Conflicts of Interest

The authors declare that there are no conflicts of interest related to the publication of this paper titled “Cat Swarm Intelligence-Driven Optimization for High Power Factor Single-Stage AC–DC Converters.” Furthermore, the authors confirm that they have no known competing financial interests or personal relationships that could have influenced the research and findings presented in this work.

 

Funding Statement

This research was conducted without any specific grant or financial support from funding agencies in the public, commercial, or not-for-profit sectors.

 

Acknowledgments

The authors sincerely acknowledge the Department of AI&DS, Mahendra College of Engineering (affiliated with Anna University), for providing the essential facilities and support that enabled the successful completion of this research. They also extend heartfelt appreciation to their mentors and colleagues for their invaluable guidance, constructive feedback, and continuous encouragement throughout the study. Finally, the authors express gratitude to all individuals and organizations whose direct or indirect contributions made this research possible.

1.      Narimani, Mehdi and Gerry Moschopoulos, "A new interleaved three-phase single-stage PFC ac–dc converter", IEEE Transactions on Industrial Electronics, Vol.61, No.2, pp.648-654, 2014. [CrossRef] [Google Scholar] [https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=41]

2.      Narimani M and Moschopoulos G, "A new single-phase single-stage three-level power factor correction AC–DC converter", IEEE Transactions on Power Electronics, Vol.27, No.6, pp.2888-2899, 2012. [CrossRef] [Google Scholar] [https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=63]

3.      El Aroudi, Abdelali, and Mohamed Orabi, "Stabilizing technique for AC–DC boost PFC converter based on time delay feedback", IEEE Transactions on Circuits and Systems, Vol.57, No.1, pp.56-60, 2010. [CrossRef] [Google Scholar] [https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919)]

4.      Li, Chushan and Dewei Xu, "Family of Enhanced ZCS Single-Stage Single-Phase Isolated AC–DC Converter for High-Power High-Voltage DC Supply", IEEE Transactions on Industrial Electronics, Vol.64, No.5, pp.3629-3639, 2017. [CrossRef] [Google Scholar] [https://ieeexplore.ieee.org/xpl/RecesntIssue.jsp?punumber=41]

5.      Dusmez, Serkan, Xiong Li and Bilal Akin,"A fully integrated three-level isolated single-stage PFC converter", IEEE Transactions on Power Electronics, Vol.30, No.4, pp.2050-2062, 2015. [CrossRef] [Google Scholar] [https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=41]

6.      Lee, Sin-Woo and Hyun-Lark Do, "Single-stage bridgeless AC–DC PFC converter using a lossless passive snubber and valley switching", IEEE Transactions on Industrial Electronics, Vol.63, No.10, pp.6055-6063, 2016. [CrossRef] [Google Scholar] [https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=41]

7.      Castro, Ignacio, Kevin Martin, Diego G. Lamar, Manuel Arias, Marta M. Hernando, and Javier Sebastian, "Single-stage AC/DC dual inductor BCM current-fed push-pull for HB-LED lighting applications", In proceedings of IEEE Energy Conversion Congress and Exposition (ECCE), pp. 1-8, 2016. [CrossRef] [Google Scholar] [https://ieeexplore.ieee.org/xpl/conhome/7859421/proceeding)]

8.      Prasanna U.R, Singh A.K and Rajashekara K, "Novel Bidirectional Single-phase Single-Stage Isolated AC–DC Converter With PFC for Charging of Electric Vehicles", IEEE Transactions on Transportation Electrification, Vol.3, No.3, pp.536-544, 2017. [CrossRef] [Google Scholar] [https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639)]

9.      Sasidharan N and Singh J.G, "A Novel Single-Stage Single-Phase Reconfigurable Inverter Topology for a Solar Powered Hybrid AC/DC Home", IEEE Transactions on Industrial Electronics, Vol.64, No.4, pp.2820-2828, 2017. [CrossRef] [Google Scholar] [https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=41]

10.   Wang, Mengqi, Suxuan Guo, Qingyun Huang, Wensong Yu and Alex Q.Huang,"An isolated bidirectional single-stage DC–AC converter using wide-band-gap devices with a novel carrier-based unipolar modulation technique under synchronous rectification", IEEE Trans. Power Electronics, Vol.32, No.3, pp.1832-1843, 2017. [CrossRef] [Google Scholar] [https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=63)]

11.   Bodetto, Mirko, Abdelali El Aroudi, Angel Cid-Pastor, and Mohammed S. Al-Numay, "Improving the Dimming Performance of Low-Power Single-Stage AC–DC HBLED Drivers", IEEE Transactions on Industrial Electronics, Vol.64, No.7, pp.5797-5806, 2017. [CrossRef] [Google Scholar] [https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=41]

12.   Weise, Nathan D, Gysler Castelino, Kaushik Basu and Ned Mohan, "A single-stage dual-active-bridge-based soft switched ac–dc converter with open-loop power factor correction and other advanced features", IEEE Transactions on Power Electronics, Vol.29, No.8, pp.4007-4016, 2014. [CrossRef] [Google Scholar] [https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=63)]

13.   Choi, Dae-Keun and Kyo-Beum Lee, "Dynamic performance improvement of AC/DC converter using model predictive direct power control with finite control set", IEEE Transactions on Industrial Electronics, Vol.62, No.2, pp.757-767, 2015. [CrossRef] [Google Scholar] [https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=41]

14.   Ohnuma, Yoshiya and Jun-Ichi Itoh, "A novel single-phase buck PFC AC–DC converter with power decoupling capability using an active buffer", IEEE Transactions on Industry Applications, Vol.50, No.3, pp.1905-1914, 2014. [CrossRef] [Google Scholar] [https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=28)]

15.   Hafezinasab, Hamidreza, Chris Botting, Deepak Gautam and Wilson Eberle, ""Universal Input AC Three-Phase Power Factor Correction with Adaptive Intermediate Bus Voltage to Optimize Efficiency", IEEE Transactions on Industry Applications, 2018. [CrossRef] [Google Scholar] [https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=41]

16.   González-Santini, Nomar S, Hulong Zeng, Yaodong Yu and Fang Zheng Peng, "Z-source resonant converter with power factor correction for wireless power transfer applications", IEEE Transactions on Power Electronics, Vol.31, No.11, pp.7691-7700, 2016. [CrossRef] [Google Scholar] [https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=63]

17.   Durgadevi, Subbiah, and Mallapu Gopinath Umamaheswari. "Analysis and design of single phase power factor correction with DC–DC SEPIC Converter for fast dynamic response using genetic algorithm optimized PI controller", IET Circuits, Devices & Systems, Vol.12, No.2, pp.164-174, 2017. [CrossRef] [Google Scholar] [https://ietresearch.onlinelibrary.wiley.com/journal/1751858x)]

18.   Poorali, Behzad and Ehsan Adib, "Analysis of the Integrated SEPIC-Flyback Converter as a Single-Stage Single-Switch Power-Factor-Correction LED Driver", IEEE Transactions on Industrial Electronics, Vol.63, No.6, pp.3562-3570, 2016. [CrossRef] [Google Scholar] [https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=41)]

19.   Durgadevi, Subbiah, and Mallapu Gopinath Umamaheswari. "Analysis and design of single-phase power factor corrector with genetic algorithm and adaptive neuro-fuzzy-based sliding mode controller using DC–DC SEPIC", An International Journal of Neural Computing and Applications, pp.1-12, 2018. [CrossRef] [Google Scholar] [https://link.springer.com/journal/521)]

20.   Kessal, Abdelhalim, and Lazhar Rahmani, "Ga-optimized parameters of sliding-mode controller based on both output voltage and input current with an application in the PFC of AC/DC converters", IEEE Transactions on Power Electronics, Vol.29, No.6, pp.3159-3165, 2014. [CrossRef] [Google Scholar] [https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=63]

21.   Samsudin N.A, Ishak D and Ahmad A.B, "Design and experimental evaluation of a single-stage AC/DC converter with PFC and hybrid full-bridge rectifier", An International Journal of Engineering science and technology, Vol.21, No.2, pp.189-200, 2018. [CrossRef] [Google Scholar] [https://www.sciencedirect.com/journal/engineering-science-and-technology-an-international-journal)]

22.   Benyamina, Abderrahmen, Samir Moulahoum, Ilhami Colak and Ramazan Bayindir, "Design and real time implementation of adaptive neural-fuzzy inference system controller based unity single phase power factor converter", An International Journal of Electric Power Systems Research, Vol.152, pp.357-366, 2017. [CrossRef] [Google Scholar] [https://www.sciencedirect.com/journal/electric-power-systems-research)]

23.   Badawy, Mohamed O, Yilmaz Sozer and J.Alexis De Abreu-Garcia, "A novel control for a cascaded buck–boost PFC converter operating in discontinuous capacitor voltage mode", IEEE Transactions on Industrial Electronics, vol.63, No.7, pp.4198-4210, 2016. [CrossRef] [Google Scholar] [https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=41]

24.   Wu H, Zhang Y and Jia Y, "Three-Port Bridgeless PFC-Based Quasi Single-Stage Single-Phase AC–DC Converters for Wide Voltage Range Applications" IEEE Transactions on Industrial Electronics, Vol.65, No.7, pp.5518-5528, 2018. [CrossRef] [Google Scholar] [https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=41]

25.   Alam, Muntasir, Wilson Eberle, Deepak S. Gautam, Chris Botting, Nicholas Dohmeier and Fariborz Musavi, "A hybrid resonant pulse-width modulation bridgeless AC–DC power factor correction converter", IEEE Transactions on Industry Applications, Vol.53, No.2, pp.1406-1415, 2017. [CrossRef] [Google Scholar] [https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=41]

26.   Lim, Seungbum, David M. Otten and David John Perreault, "New AC–DC power factor correction architecture suitable for high-frequency operation", IEEE Transactions on Power Electronics, Vol.31, No.4, pp.2937-2949, 2016. [CrossRef] [Google Scholar] [https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=63]

27.   Liu, Xueshan, Jianping Xu, Zhangyong Chen and Nan Wang, "Single-Inductor Dual-Output Buck-Boost Power Factor Correction Converter", IEEE Trans. Industrial Electronics, Vol.62, No.2, pp.943-952, 2015. [CrossRef] [Google Scholar] [https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=41]

28.   Zeng, Guo-Qiang, Jie Chen, Yu-Xing Dai, Li-Min Li, Chong-Wei Zheng and Min-Rong Chen, "Design of fractional order PID controller for automatic regulator voltage system based on multi-objective extremal optimization", An International Journal of Neurocomputing, Vol.160, pp.173-184, 2015. [CrossRef] [Google Scholar] [https://www.sciencedirect.com/journal/neurocomputing)]

29.   Sharma, Richa, Prerna Gaur and A. P. Mittal, "Performance analysis of two-degree of freedom fractional order PID controllers for robotic manipulator with payload", ISA transactions, Vol.58, pp.279-291, 2015. [CrossRef] [Google Scholar] [https://www.sciencedirect.com/journal/isa-transactions)]

30.   Guo, Lei, Zhuo Meng, Yize Sun and Libiao Wang, "Parameter identification and sensitivity analysis of solar cell models with cat swarm optimization algorithm", An International Journal of Energy conversion and management, Vol.108, pp.520-528, 2016. [CrossRef] [Google Scholar] [https://www.sciencedirect.com/journal/energy-conversion-and-management)]

31.   Mohapatra, P., Sreejit Chakravarty and P. K. Dash, "Microarray medical data classification using kernel ridge regression and modified cat swarm optimization based gene selection system", An International Journal of Swarm and Evolutionary Computation, Vol.28, pp.144-160, 2016. [CrossRef] [Google Scholar] [https://www.sciencedirect.com/journal/swarm-and-evolutionary-computation)]

32.   Yang, Feng, Mingyue Ding, Xuming Zhang, Wenguang Hou and Cheng Zhong. "Non-rigid multi-modal medical image registration by combining L-BFGS-B with cat swarm optimization", An International Journal of Information sciences, Vol.316, pp.440-456, 2015. [CrossRef] [Google Scholar] [https://www.sciencedirect.com/journal/information-sciences)]

33.   Saravanan, G., R. Tripathy & U. R. Rao, “Cloud-IoT Framework for EV Charge Station Allocation and Scheduling: A Spotted Hyena Jellyfish Search Optimization Approach”, Sustainable Computing: Informatics and Systems, Vol. 46, p. 101118, 2025.[https://scholar.google.com/citations?hl=en&user=QmaiV2UAAAAJ&utm_source=chatgpt.com]

34.   [https://www.sciencedirect.com/science/article/abs/pii/S2210537925000381]